LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY latch IS
  PORT( d, clk : IN std_logic;
        q, qb : OUT std_logic);
END latch;

ARCHITECTURE latch_guard OF latch IS
BEGIN
  G1 : BLOCK( clk = '1')
  BEGIN
    q <= GUARDED d AFTER 5 ns;
    qb <= GUARDED NOT(d) AFTER 7 ns;
  END BLOCK G1;
END latch_guard;






