PACKAGE p_qual_2 IS    
  TYPE vector8 IS ARRAY( 0 TO 7) OF BIT; 
END p_qual_2; 

USE WORK.p_qual_2.ALL; 
ENTITY latch IS    
  PORT( reset, clock : IN BIT;          
        data_in : IN vector8;          
        data_out : OUT vector8); 
END latch; 

ARCHITECTURE behave OF latch IS 
BEGIN    
  PROCESS(clock)    
  BEGIN        
    IF (clock = '1') THEN            
      IF (reset = '1') THEN                
        data_out <= vector8'(others => '0');
      ELSE                
        data_out <= data_in;            
      END IF;        
    END IF;    
  END PROCESS; 
END behave;


