Entity test is
end test;

architecture rtl of test is

 SIGNAL instruction : BIT_VECTOR(31 DOWNTO 0);

ALIAS opcode : BIT_VECTOR(3 DOWNTO 0) IS instruction(31 DOWNTO 28);
ALIAS src_reg : BIT_VECTOR(4 DOWNTO 0) IS instruction(27 DOWNTO 23);
ALIAS dst_reg : BIT_VECTOR(4 DOWNTO 0) IS instruction(22 DOWNTO 18);

-- ALIAS vhdl93 is instruction(0 to 3);

begin

end rtl;


