LIBRARY IEEE; 
USE IEEE.std_logic_1164.ALL;
ENTITY and5 IS
  PORT ( a, b, c, d, e : IN  std_logic;
         q : OUT std_logic);
END and5;

ARCHITECTURE and5 OF and5 IS
BEGIN
  PROCESS(a, b, c, d, e)
    VARIABLE state : std_logic;
    VARIABLE delay : time;
  BEGIN

    state := a AND b AND c AND d AND e;

    IF state = '1' THEN
      delay := 4.5 ns;
    ELSIF state = '0' THEN
      delay := 3 ns;
    ELSE
      delay := 4 ns;
    END IF;

    q <= state AFTER delay;

  END PROCESS;
END and5;


