LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff_pc IS
  PORT( preset, clear, clock, din : IN std_logic;
        dout : OUT std_logic);
END dff_pc;

ARCHITECTURE synth OF dff_pc IS
BEGIN
  PROCESS(preset, clear, clock)
  BEGIN
    IF (preset = '1') THEN
      dout <= '1';

    ELSIF (clear = '1') THEN
      dout <= '0';

    ELSIF (clock'EVENT) AND (clock = '1') THEN
      dout <= din;

    END IF;
  END PROCESS;
END synth;

