LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
ENTITY adder IS
   PORT( a,b : IN std_logic_vector(7 DOWNTO 0);
              c : OUT std_logic_vector(7 DOWNTO 0)
            );
END adder;

ARCHITECTURE test OF adder IS
BEGIN
   c <= a + b;
END test;


