LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
PACKAGE bit32 IS
  TYPE tw32 IS ARRAY(31 DOWNTO 0) OF std_logic;
END bit32;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE WORK.bit32.ALL;
ENTITY cpu IS
  PORT( clk, interrupt : IN std_logic;
        addr : OUT tw32; data : INOUT tw32 );
END cpu;

ARCHITECTURE cpu_blk OF cpu IS
  SIGNAL ibus, dbus : tw32;
BEGIN
  ALU : BLOCK 
    SIGNAL qbus : tw32;
  BEGIN
    -- alu behavior statements
  END BLOCK ALU;

  REG8 : BLOCK
    SIGNAL zbus : tw32;
  BEGIN
    REG1: BLOCK
      SIGNAL qbus : tw32;
    BEGIN
      -- reg1 behavioral statements
    END BLOCK REG1;

    -- more REG8 statements

  END BLOCK REG8;
END cpu_blk;

