ENTITY and2 IS
  PORT ( a, b : IN BIT;
         c : OUT BIT );
END and2;

ARCHITECTURE and2_behav OF and2 IS
BEGIN
  c <= a AND b AFTER 5 ns;
END and2_behav;



ENTITY and2 IS
  GENERIC(rise, fall : TIME; load : INTEGER);
  PORT( a, b : IN BIT;
           c : OUT BIT);
END AND2; 


ARCHITECTURE load_dependent OF and2 IS
  SIGNAL internal : BIT;
BEGIN
  internal <= a AND b;
  c <= internal AFTER (rise + (load * 2 ns)) WHEN internal = '1'
    ELSE internal AFTER (fall + (load * 3 ns));

END load_dependent;
