ENTITY reg IS
  PORT( a, clock : in bit;
        d : out bit);
END reg;

ARCHITECTURE test OF reg IS
  SIGNAL b, c : bit;
BEGIN
  b <= NOT(a);  -- notice no delay
  c <= NOT( clock AND b);
  d <= c AND b;
END test;


-------- added to compile architecture
-------- below
--------------------------------------
entity test is
  port(b, c : in bit;
       a : out bit);
end test;
--------------------------------------

ARCHITECTURE test OF test IS
BEGIN
--  a <= b AFTER 10 ns;
  a <= c AFTER 10 ns;
END test;
