LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL; 
ENTITY nand2 IS
  PORT( a, b : IN std_logic;
        c : OUT std_logic);
END nand2;

ARCHITECTURE nand2 OF nand2 IS
BEGIN
  PROCESS( a, b )
    VARIABLE temp : std_logic;
  BEGIN
    temp := NOT (a and b);

    IF (temp = '1') THEN
      c <= temp AFTER 6 ns;
    ELSIF (temp = '0') THEN
      c <= temp AFTER 5 ns;
    ELSE
      c <= temp AFTER 6 ns;
    END IF;

  END PROCESS;
END nand2; 

