------------------------------------------------------
--- added to make below compile
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity test is
  port(clk, trigger1, trigger2, trigger3 : in std_logic);
end test;
------------------------------------------------------
ARCHITECTURE test OF test IS
  TYPE t_int is (int1, int2, int3, int4, int5 );

  SIGNAL int, intsig1, intsig2, intsig3 : t_int;

  SIGNAL lock_out : BOOLEAN;
BEGIN
  int1_proc: PROCESS
  BEGIN
    --
    --
    --
    WAIT ON trigger1;  -- outside trigger signal
    WAIT UNTIL clk = '1';
      IF NOT(lock_out) THEN
        intsig1 <= int1;
      END IF;
  END PROCESS int1_proc;

  int2_proc: PROCESS
  BEGIN
    --
    --
    --
    WAIT ON trigger2;  -- outside trigger signal
    WAIT UNTIL clk = '1';
      IF NOT(lock_out) THEN
        intsig2 <=int2;
      END IF;
  END PROCESS int2_proc;

  int3_proc: PROCESS
  BEGIN
    --
    --
    --
    WAIT ON trigger3;-- outside trigger signal
    WAIT UNTIL clk = '1';
      IF NOT(lock_out) THEN
        intsig3 <=int3;
      END IF;
  END PROCESS int3_proc;

  int <=intsig1 WHEN NOT(intsig1'QUIET) ELSE
        intsig2 WHEN NOT(intsig2'QUIET) ELSE
        intsig3 WHEN NOT(intsig3'QUIET) ELSE
        int;

  int_handle : PROCESS
  BEGIN
    WAIT ON int'TRANSACTION;-- described next
    lock_out <= TRUE;
    WAIT FOR 10 ns;
    CASE int IS
      WHEN int1 =>
        --
        --
      WHEN int2 =>
        --
        --
      WHEN int3 =>
        --
        --
      WHEN int4 =>
        --
        --
      WHEN int5 =>
        --
        --
    END CASE;
    lock_out <= false;
  END PROCESS;
END test;


