LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff_asynch IS
  PORT( clock, reset, din : IN std_logic;
        dout : OUT std_logic);
END dff_asynch;

ARCHITECTURE synth OF dff_asynch IS
BEGIN
  PROCESS(reset, clock)
  BEGIN
    IF (reset = '1') THEN
      dout <= '0';
    ELSIF (clock'EVENT) AND (clock = '1') THEN
      dout <= din;
    END IF;
  END PROCESS;
END synth;

