ENTITY datadelay IS
   PORT( clk, din, en : IN BIT;
                 dout : OUT BIT);
END datadelay;

ARCHITECTURE inference OF datadelay IS
   SIGNAL q1, q2 : BIT;
BEGIN
   reg_proc: PROCESS
   BEGIN
   
      WAIT UNTIL clk'EVENT and clk = '1';

      q1 <= din;
      q2 <= q1;

   END PROCESS;

   dout <= q1 WHEN en = '1' ELSE
                  q2;
END inference;

