PACKAGE mux_types IS
  SUBTYPE eightval IS INTEGER RANGE 0 TO 7; -- line 1
END mux_types;

USE WORK.mux_types.ALL;
LIBRARY IEEE; 
USE IEEE.std_logic_1164.ALL;
ENTITY mux8 IS
  PORT(I0, I1, I2, I3, I4, I5,
       I6, I7: IN std_logic;
       sel : IN eightval; -- line 2 
       q   : OUT std_logic);
END mux8;

ARCHITECTURE mux8 OF mux8 IS
BEGIN
  WITH sel SELECT   -- line 3
      Q <= I0 AFTER 10 ns WHEN 0, -- line 4
           I1 AFTER 10 ns WHEN 1, -- line 5
           I2 AFTER 10 ns WHEN 2, -- line 6
           I3 AFTER 10 ns WHEN 3, -- line 7
           I4 AFTER 10 ns WHEN 4, -- line 8
           I5 AFTER 10 ns WHEN 5, -- line 9
           I6 AFTER 10 ns WHEN 6, -- line 10
           I7 AFTER 10 ns WHEN 7; -- line 11
END mux8;




