LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY dff IS
  PORT( clock, din : IN std_logic;
        dout : OUT std_logic);
END dff;

ARCHITECTURE synth OF dff IS
BEGIN
  PROCESS
  BEGIN
    WAIT UNTIL ((clock'EVENT) AND (clock = '1'));

    dout <= din;

  END PROCESS;
END synth;

