# Release Notes for the 2002.1E Release

## Table of Contents

1. Release Version
2. New Features And Improvements
3. Changes in Functionality
4. New or Changed Commands
5. Fixed Bugs
6. Known Limitations
7. Contact Information

## 1. Release Version

Bridges2Silicon Debugger Release 2002.1E was built on March 19th, 2002.

## 2. New Features And Improvements

### 2.1 Altera Builtin JTAG Support

For Altera APEX devices users now can connect the Bridges2Silicon Debugger via the APEX device's builtin JTAG port. The connection is performed via the Altera Quartus JTAG Server which requires the availability of QuartusII Version 2.0 at run-time of the Bridges2Silicon Debugger.

## 3. Changes in Functionality

With respect to Release 2002.1C there are no changes in functionality.

## 4. New or Changed Commands

No commands have been changed or added with respect to Release 2002.1C

## 5. Fixed Bugs

The HDL style of the IICE implementation which is written our as the result of the instrumentation has been changed. These changes aim to fix several potential problems with certain synthesis tools.

## 6. Known Limitations

### 6.1. VHDL/Verilog Folded Hierarchy Support

A design may have hierarchical blocks (VHDL entities, Verilog modules) which are instantiated more than once. Our tool is neutral to such "folded hierarchy". However, currently elements within such a folded hierarchical block cannot be instrumented.

The work-around for this limitation is to "unfold the hierarchy" by duplicating the HDL code for this hierarchical block such that each duplicate block gets instantiated only once.

### 6.2. Verilog wor/wand support

Verilog wand/wor/... are currently treated as wires. Support for Verilog wand/wor/... is planned for future releases.

### 6.3. Sample Depth Values

Due to the speed-optimized pipelined architecture of the IICE, sample data are delayed by a certain number of sample clock cycles. In order to see the sample data at the time of triggering, the sample depth should be larger or equal 8.

### 6.4. Verilog Include Files with Absolute Paths

There is a known problem with instrumenting the contents within Verilog files which get included via an absolute path name. When writing out the instrumented design, the Instrumentor cannot adjust such absolute include paths. As a result, the instrumented design files will -- incorrectly -- refer to the original include files. This may result in synthesis errors and incorrect behavior of the IICE.

The work-around is NOT TO USE ABSOLUTE PATH NAMES when including Verilog files. Rather use relative path names to include Verilog design files.

### 6.5. Windows Design Files from Multiple Drives

There is a known problem under Windows (all supported versions) with handling designs files which originate from more than one single drive. When writing out the instrumented design, the Instrumentor cannot compute a common path component for the instrumented design files. This results in an error message of the Instrumentor and no instrumented design files will be written.

On Windows the work-around is to put all design files into one single drive, for example the D: drive.

### 6.6. VHDL Partial Assignment to Aliases

The Instrumentor VHDL front-end does not support partial assignment to aliases. Support for this is planned for future releases.

If the HDL code cannot be altered, a possible work-around is to "blackbox" the entities which contain such statements. However, blackboxed entities cannot be instrumented.

## 7. Contact Information

Bridges2Silicon, Inc.
Customer Support
471 East Evelyn Ave
Sunnyvale, CA 94086
Phone +1 (408) 245 8513
Fax +1 (408) 245 2960
Email: support@bridges2silicon.com
Web: http://www.bridges2silicon.com

To obtain a license keys please contact the friendly Bridges2Silicon Team and request an evaluation license key via our web site.

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